1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device having a circuit composed of a thin film transistor (hereafter, referred to as TFT), and in particular to a manufacturing method of a semiconductor device having a gate electrode wiring of a forwardly tapered shape which is obtained by photolithography processing and dry etching processing.
2. Related Art
Recently, electrooptical devices such as active matrix type liquid crystal display device, which performs active matrix display using a TFT, have been drawing public attention. The electrooptical device, which performs active matrix display, is provided with a TFT switch to each electrooptical device and state of crystal orientation of TN (abbreviation of Twisted-Nematic) mode can be utilized. Compared to a passive matrix display, since the active matrix display has advantages in the points of response speed, angle of visibility and contrast, it has become a major trend in the current notebook-sized personal computers, liquid crystal TVs and the like.
Generally, in the TFT, amorphous silicon or polycrystalline silicon is used as the channel layer thereof. Particularly, the polycrystalline silicon TFT, which is manufactured by means of low-temperature processing (generally, lower than 600° C.), is in a trend of being reduced in price and being enlarged in size. Electron or positive hole of the polycrystalline silicon TFT has large electric field mobility. Accordingly, when the TFT is used in a liquid crystal display device, since it is possible to integrate not only the transistor for pixel but also the driver, which is a peripheral circuit thereof, each maker of liquid crystal display device has promoted its development. However, when the polycrystalline silicon TFT is driven for a long period of time, sometimes such problems concerning reliability that decrease of mobility or ON-current (current which flows when the TFT is ON), increase of OFF-current (current which flows when the TFT is OFF) or the like are found. These phenomena are called as hot carrier effect, and it is known that these phenomena are caused by hot carrier that is generated due to high electric field in the area adjacent to the drain.
On the other hand, in MOS transistor of 1.5 μm in design rule, as a technique for buffering the OFF-current and the high electric field adjacent to the drain, an LDD (abbreviation of Lightly-Doped-Drain) structure is adopted. The LDD structure of NMOS transistor is formed by providing an n-type low-density impurity area (n−area) to the edge area of the drain using the side wall of the gate to provide a taper to the density of the impurity of the drain junction, and thereby, the concentration of electric field in the area adjacent to the drain is buffered. However, compared to the single drain structure, in the LDD structure, although the drain withstand voltage is considerably increased, since the resistance of the n−area is large, such disadvantage that drain current is decreased remains. Further, high electric field area exists under the side wall, the collision electrolytic dissociation reaches the maximum there, and hot electron is injected into the side wall. As a result, such problems of deterioration mode peculiar to the LDD that the n−area is depleted, and further, resistance is increased have emerged. Since the above-described problems have emerged accompanying the reduction of channel length, in the NMOS-transistor of 0.5 μm or less, GOLD (abbreviation of Gate-Overlapped-LDD) structure, in which the n−area is formed being overlapped with the edge area of the gate electrode, has been developed as a structure for solving the problem, and is now promoted to put into the actual mass production.
Under such circumstances as described above, in the n-channel polycrystalline silicon TFT also, in order to buffer the high electric field in the area adjacent to the drain, it is considered to apply the GOLD structured TFT. For example, an example of the application of the GOLD structured TFT is disclosed in IEDM97 TECHNICAL DIGEST; P523–526, 1997; Mutuko Hatano, Hajime Akimoto and Takesi Sakai. In the above-described GOLD structured TFT, the side wall for LDD of the polycrystalline gate is formed with polycrystalline silicon, and in the active layer comprised of poly-crystalline silicon layer immediately under the sidewall for LDD, a low-density impurity area (n−area), which functions as the electric field buffer area, is formed. Further, at the outside area of the low-density impurity area (n−area), a high-density impurity area (n+area), which functions as the source area and drain area, is formed. As described above, in the GOLD structured TFT, it is characterized by that the low-density impurity area (n−area) is formed being overlapped with the edge area of the gate electrode.
In the manufacturing method of a GOLD structured TFT, as for the method of forming the high-density impurity area (n+area) and the low-density impurity area (n−area), a method in which the impurity areas are formed with resist mask only; and another method in which, using the gate electrode as the mask, the impurity areas are formed in a manner of self-matching are known. In the former method in which the impurity areas are formed using the resist mask only, since the photolithography process for forming the resist mask is required to carry out twice, the increase in photolithography processes is a large disadvantage. On the other hand, in the latter method in which, using the gate electrode as the mask, the impurity areas are formed in a manner of self-matching, such an advantage that the photolithography process is prevented from increasing is provided, and that is advantageous for mass production processing.
As described above, in the polycrystalline silicon TFT, the GOLD structured TFT is taken into consideration. And as for the processing of the gate electrode of the GOLD structured TFT, the photolithography process using a positive type resist of diazonaphthoquinone (DNQ)-novolac resin series, which is generally used in semiconductor processing, and the etching process by means of dry etching are taken into consideration.
In the photolithography process using a positive type resist of diazonaphthoquinone (DNQ)-novolac resin series, as the preventive measures against halation phenomenon, conventionally, a method in which a photo-absorbent composed of dye is added to the resist material is known. The halation phenomenon is a phenomenon, in which the resist in unexposed area is locally exposed undesirably by the reflected light from the tapered shoulder portion of the high reflective base substrate resulting in a local thinness of the resist pattern. When adding the photo-absorbent to the resist material to prevent the halation phenomenon, if the added amount of the photo-absorbent is too small, the preventive effect against the halation phenomenon cannot be obtained satisfactorily. On the other hand, if the added amount of the photo-absorbent is too large, although the preventive effect against the halation phenomenon can be obtained satisfactorily, the absorbance of the resist material becomes too large resulting in such disadvantage that the taper angle of the side wall of the resist pattern decreases. Accordingly, when the photo-absorbent is added to the resist material as the preventive measures against the halation phenomenon, it is necessary to control the density of the photo-absorbent to an adequate level.
Referring to FIG. 5-F and FIG. 6-F showing an example of a GOLD structured TFT respectively, the GOLD structured TFT is constituted of a gate electrode which is comprised of a first layer gate electrode and a second layer gate electrode on the above-described first layer gate electrode. Compared to the second layer gate electrode, the first layer gate electrode is characterized in that it is formed thinner in film thickness and longer in dimension of the channel direction. The GOLD structured TFT is formed by laminating gate insulating film 203e, 303e respectively, being interposed by a semiconductor layer comprised of a polycrystalline silicon film on an insulative substrate such as a glass substrate or the like, and a first layer gate electrode 204e, 304e, which is thinner in film thickness and longer in dimension of the channel direction and a second layer gate electrode 205e, 305e, which is thicker in film thickness and shorter in dimension of the channel direction, are laminated thereon. And in the semiconductor layer, which is covered by the first layer gate electrode 204e, 304e, where is thin in film thickness and long in dimension in the channel direction, i.e., in the semiconductor layer corresponding to the area where the first layer gate electrode 204e, 304e is exposed from the second layer gate electrode 205e, 305e, an n-type low-density impurity area (n−area), which functions as the electric field buffer area, is formed so as to overlap with the gate electrode; and is named as Lov area 208, 309 respectively in FIGS. 5-F and 6-F. In the outside area of the Lov areas 208, 309, in the same manner as the above, an n-type low-density impurity area (n−area), which functions as the electric field buffer area, is formed so as not to overlap with the gate electrode; and is named as Loff areas 209, 310 respectively in FIGS. 5-F and 6-F. Furthermore, in the outside area of the Loff area 209, 310, an n-type high-density impurity area (n+area) 207, 307, which functions as the source area and drain area, is formed respectively (refer to FIGS. 5-F, 6-F).
In the GOLD structured TFT of n-type channel structured as described above, in order to increase the reliability of the GOLD structured TFT, it is preferred that the Lov area 208, 309, which overlaps with first layer gate electrode 204e, 304e, is longer. However, on the other hand, when the Lov area 208, 309 is too long, such disadvantage that the parasitic capacity increases remains. Accordingly, it is required to control the Lov area 208, 309 to an adequate dimension. The dimension of the Lov area 208, 309 is equal to that of the area where is covered by the first layer gate electrode 204e, 304e, i.e., the area where the first layer gate electrode 204e, 304e is exposed out of the second layer gate electrode 205e, 305e. Furthermore, the dimension of the Lov area 208, 309 is determined depending on the retreat amount of the resist pattern 206a, 306a in taper etching by means of resist-retreating method. Accordingly, to control the dimension of the Lov area 208, 309, it is necessary to control the retreat amount of the resist pattern 206a, 306a in taper etching, and it is known that the retreat amount of the resist is controlled by the taper angle of the side wall and the dry etching conditions of the resist pattern 206a, 306a, which is used as the mask in dry etching (refer to FIGS. 5-F, 6-F).
However, in the conventional configuration of the resist pattern 206a, 306a, the taper angle of the side wall of the resist pattern is larger than the desired taper angle in the range of 90° or less. Accordingly, it is difficult to obtain a desired retreat amount of the resist unless the loss in quantity of the resist film is increased by setting the dry etching conditions to a severer level. Also, as a result, it is difficult to form the Lov area 208, 309 of desired dimension. On the other hand, when the dry etching conditions are set to a severer level, it is foreseeable that it works adversely with respect to the break of the gate insulating film in the GOLD structured TFT from the viewpoint of the processing margin. As described above, in the conventional technique, such problem remains that it is difficult to form the Lov area 208, 309 to a desired dimension from the viewpoint of the processing margin (refer to FIGS. 5-F, 6-F).
An object of the invention is to solve the above-described problems of the conventional technique, more particularly, to solve the problems with respect to the processing margin in forming the Lov area of a GOLD structured TFT.